In designing an integrated electrical circuit, the circuit is expected to satisfy certain user-specified requirements. The creation of a complex circuit may involve creation of a topology, component sizing and placement, and also routing of wires that interconnect the circuit components.
By ‘sizing’ is meant assigning values to the circuit's components. By ‘placement’ is meant assignment to the circuit's components a particular physical location on; e.g., a printed circuit board or a silicon wafer. Placement data may, therefore, represent spatial coordinates (e.g., Xi; Yi) of the components. By ‘routing’ is meant assignment of a particular physical location to the wires in the circuit and, in particular, to the interconnection of wires between the leads of the circuit's components.
The physical location of each component and wire may affect the overall behavior of all circuits to some extent because electrical components may have interaction with one another based on their physical location. The electrical coupling between adjacent components, signal wiring and IC substrate, generally called parasitic effects, are generally small and may not be important to the performance of ‘simple’ circuits operating at relatively low frequencies. In such cases, parasitic effects may simply be factored out. By ‘parasitic effect’ is meant undesired effect caused by capacitance, resistance, and sometimes inductance, which are introduced by interconnecting adjacent wires. However, parasitic effects may detrimentally impact the performance of a more complex circuit or a circuit operating at relatively high frequencies, for example, at radio frequencies (“RF”). Under such circumstances, it may be impossible to design a practical circuit without factoring in probable parasitic effects.
Interconnection wirings may affect different circuits in different ways. For example, synchronization is essential for the proper functionality of many digital circuits. However, ‘bad’ wiring routing may ‘force’ the circuit out of synchronization because it may undesirably impact the time required for an electrical signal to travel between two components along a certain wire or wiring path.
With the ongoing miniaturization of semiconductor components and integrated circuits into the nanometer domain in past years, the importance and affect of parasitic effects upon the design of a circuit is constantly increasing. This is, due to the fact that at smaller scales, previously unimportant parasitic effects are now magnified. Therefore, when designing microelectronic circuit, a microelectronics engineer has an additional task, which is to find ways to minimize and overcome these effects while always delivering smaller and faster components.
Because parasitic effects can render microelectronic circuits useless, if ignored or mishandled, a validation process is included in the layout-designing phase of IC circuits. Typically, a validation process includes the performance of iterative steps, elements resizing in the schematic level, layout adjustments (of both components' placement and their interconnectivity), parasitic information extraction, post-layout timing analysis and layout returning. A parasitic extraction process analyzes the layout and, based on geometry and technology properties, creates additional simulation models, which are then used in circuit timing analysis.
Timing closure of large full custom circuits in sub-micron technologies operating at GHz frequencies has become a lengthy process that typically involves many iterative steps. The timing closure phase, which is required to evaluate the performance of the IC circuit, involves the evaluation of temporal delays caused by parasitic effects of interconnection wirings and, sometimes, by “via” connections between different signal layers. The association between wires (and, where relevant, “via” connections between layers) to the delays they cause is sometimes referred to as “delay models”, or “wire models”.
Traditional systems used for circuit design suffer from several drawbacks. In order to elaborate on these drawbacks, a reference is made now to FIG. 1.
FIG. 1 exemplifies a traditional full custom circuit design flow. At step 101, after the logical design of the full custom circuit is completed, a first data file is generated that represents, inter alia, the original schematic design of the integrated circuit. The original schematic design file (herein simply ‘schematic design file’) may be generated using traditional methods.
The various circuit components are initially sized, at step 102, and a preliminary timing analysis is performed, at step 103, based mainly on intuition, and/or guesswork, and/or accumulative experience in the field of IC design. The first data file may also include data relating to the size of the various components of the circuit. The preliminary timing analysis is typically implemented by manually adding wire model objects to the circuit schematics (more specifically to the first schematic file). Being inserted manually, delay models can be used only in respect of a relatively small number of wires. For this reason, a circuit designer has first to intuitively identify wires as ‘critical wires’ and then construct wire models in respect of the ‘critical’ wires.
The latter conduct is problematic in two aspects. First, the circuit designer may erroneously consider non-critical wires as critical. Secondly, the circuit designer may inadvertently ignore ‘real’ critical wires. Therefore, using delay models in the traditional manner is far from being an adequate solution for a circuit that consists of many components (e.g., logic gates). Put simply, it is impractical to manually construct an accurate delay model for a large number of wires. Therefore, in placing the circuit's components, at step 104, only an incomplete ‘picture’ of the parasitic effects is factored in, which ill affects the other processes involved in the circuit design by rendering them very lengthy and troublesome, as explained hereinafter. Partial solution to this problem involves repeating steps 102 and 103 (103/1), though using, wire model objects in the traditional manner (at step 103) cannot significantly shorten the circuit's designing process or mitigate the drawbacks associated with it.
Then, the circuit's components, each assigned an initial size (102), are physically placed, at step 104, and routed, at step 105, to form the layout of the circuit. The layout is then checked, by employing one or more verification procedures known in the field as design rule checking (“DRC”), layout versus schema (“LVS”) and methodology checks (“METH”). Briefly, DRC generally concerns checking the conformity to technology constraints, or to design rules. LVS generally concerns checking equivalency between the layout and the schema. METH generally concerns conformity to methodology constraints.
If the layout meets the requirements/constraints at step 106, an “extraction” stage is performed, at step 107, in which the candidate circuit's layout is converted into a ‘netlist’, which includes all circuit components and interconnect (wiring) parasitics at step 107.
Then, a post layout timing analysis is performed, at step 108, for evaluating the real time performance of the circuit. If the layout (106) fails to satisfy the timing analysis at step 108, components of the circuit are re-sized, at step 109, re-placed, at step 110 and re-routed, at step 111. Then, the resulting layout is checked (112), its parasitics are extracted (113) and it undergoes a final timing analysis (114), the procedures 112 to 114 being similar to the procedures 106, 107 and 108, respectively. The latter three steps (112 to 114) may be collectively thought of as a “validation procedure” (118). If a layout successfully passes the validation procedure (118), it is considered a “final layout” (115) that may be used for mass fabrication. However, if the layout (112) is invalidated, components are, again, re-sized (109), re-placed (110) and re-routed (111). Timing closure loop 116 continues until final layout results.
Simulating a circuit (i.e., testing it in the schematic level) is preferable over testing physical circuit layout, both in time and costs. In respect of this it is noted that both the post layout timing analysis and the final timing analysis are done in respect of the layout of the (i.e., physical) circuit. It is also noted that wire model objects are used only in a very early stage of the designing process (at step 103), with all the drawbacks described herein and before routing issues are addressed (at step 105).
As explained hereinbefore, because only critical wires are modeled (103), comprehensive timing analysis cannot be accurately performed in the schematic level. Therefore, accurate timing closure cannot be achieved in the schematic level but, rather, it is performed only at a post layout process (at step 108), which is relatively a late stage in the IC's designing process. Having to time-wise analyze circuit layouts, rather than circuit schematics, results in executing many lengthy processes (i.e., 106 to 108, and 112 to 114) before a decision may be reached as to whether another iteration (116) should be made in trying to converge to a feasible layout that meets the required circuit performance.
Therefore, every optimization iteration, or loop (116), takes a considerable amount of time. In addition, due to the incomplete ‘picture’ of the parasitic effects many iterations (116) are executed before reaching time closure on a feasible circuit layout. Depending on the circuit complexity, optimization iterations through full layout design cycles (116) may take very long time (e.g., several weeks).
Therefore, a need exists for enhancing the design process associated with circuit layout design. Another need exists for significantly reducing the time period required to design a large full custom circuit. A further need exists for allowing running accurate timing simulations on the schematic level. A further need exists for reducing the number of iterations involved in the layout design and validation process and also to reduce the duration of each iteration.